Esd-robust power switch and method of using same

ABSTRACT

A power switch comprising a field effect transistor (FET) including an active area in a semiconductor body, a channel formed in said active area and having a periodic structure, source diffusion zones and drain diffusion zones in the active area, a source diffusion zone being separated from a drain diffusion zone by a half period of the periodic structure of the channel, and each source diffusion zone having a source contact, and each drain diffusion zone having a drain contact. The source contacts and the drain contacts are aligned in a row in a direction transverse to the plane of symmetry of the channel. Current paths have substantially the same series resistance between a source contact and a drain contact associated with a source diffusion zone and a drain diffusion zone which alternate with each other. The ESD-robust power switch is very compact and suited for high voltages.

The invention relates to a power switch comprising a field effecttransistor (FET) including

-   -   an active area in a semiconductor body,    -   a channel formed in said active area and having a periodic        structure,    -   source diffusion zones and drain diffusion zones in the active        area, a source diffusion zone being separated from a drain        diffusion zone by a half period of the periodic structure of the        channel, and    -   each source diffusion zone having a source contact, and each        drain diffusion zone having a drain contact.

The invention also relates to a method of using the power switch inaccordance with the invention.

U.S. Pat. No. 6,002,156 discloses such a MOSFET that protects anintegrated circuit (IC) against electrostatic discharge(ESD)/electrostatic overstress (EOS). The integrated circuit is an ICwith MOS transistors. The most common protection circuit for ICs withMOS transistors is an NMOS transistor whose drain is connected to thepin to be protected of the IC and whose source and gate are connected toground. The protection level can be adjusted through the width of thechannel of the NMOS. Under voltage conditions, the parasitic bipolartransistor of the NMOS transistor is the dominant current path betweenthe pin to be protected and ground. This bipolar transistor operates inthe snap-back region when the pin voltage is positive with respect toground.

The known MOSFET has a compact layout. The channel has a meanderingshape. The part of the meandering channel that is repeated in theperiodic pattern is a period. As a result of the meandering structure ofthe channel, the width of the channel per unit area is increased. Saidincrease of the width of the channel per unit area has the advantagethat the current level can be higher as a result of the ESD protection.Alternatively, said ESD protection may take up less space. In the knownembodiment, the gain in width per unit area is maximally 40%.

A drawback of the known MOSFET resides in that owing to the compactlayout only a low series resistance in the diffusion zones is possible,so that the transistor is unsuitable to deal with high voltage peaks. Inaddition the MOSFET has a high gate resistance as a result of which thedevice cannot switch rapidly and the gate voltage cannot be controlled.

To test the ESD robustness of the device, use is generally made of theHuman Body Model (HBM) and the Charged Device Model (CDM). In the HBM,simulation takes place of the discharge that may occur when a persontouches a device. The human body can be represented by a capacitor of100 pF which is charged to a specified voltage. The capacitor issubsequently discharged over the device and over a resistor of 1500 Ohm.

CDM simulates a charged device that makes contact with a metal basearea, which occurs typically in the case of automated handlingequipment.

In general, the dominant failure mechanism of an NMOS protection deviceoperating in snap-back is second breakdown. Second breakdown is aphenomenon that induces thermal runaway into the device when thedecrease of the impact ionization current is negligible with respect tothermal generation of charge carriers. Second breakdown occurs in thecase of a high current through the device as a result of self-heating.The time that is necessary to heat up the structure to the criticaltemperature at which second breakdown occurs depends on the devicelayout and on the stress power distribution over the device.

It is an object of the invention to provide a power switch of the typedescribed in the opening paragraph, which is more robust to voltagepeaks.

In the case of the power switch in accordance with the invention, thisobject is achieved in that the source contacts and the drain contactseach form a row in a direction transverse to the plane of symmetry ofthe channel, current paths being subject to substantially equal seriesresistance between a source contact and a drain contact associated witha source diffusion zone and a drain diffusion zone which alternate witheach other.

The series resistance makes sure that if a part of the transistor goesinto snap-back and causes the drain voltage to be reduced, the voltagethat can be built up in the case of an increasing current across theseries resistance is sufficient so that the trigger voltage for thesnap-back of another part of the transistor can be achieved againwithout the current density locally increasing to destructive values.

As a result of equal series resistances in the current paths between asource contact and a drain contact of each diffusion zone, the currentis distributed more uniformly over the entire active area. The improvedspread of the ESD current leads to a more uniform distribution of theheat, as a result of which local heating is reduced and second breakdownoccurs less readily. In comparison with the prior art, the FET is moresuitable to deal with higher voltage peaks of typically 2000-8000 V(HBM) and is also more suitable to drain a higher ESD current to ground.

Preferably, the row of source contacts and the row of drain contacts aresituated outside an area that is clamped by the periodic structure ofthe channel. By spacing the contacts relatively far apart, a seriesresistance is created. The series resistance between the source anddrain contacts can be accurately adjusted through the distance betweenthe row of source contacts and the row of drain contacts. In order notto adversely affect the switching behavior of the FET, the seriesresistance is only a small percentage of the on-resistance of thetransistor. However, to withstand high voltage peaks and to be capableof safely draining to ground the associated ESD current, the seriesresistance must be large enough. In practice, the series resistance istypically of the order of 10% of the on-resistance of the transistor.The series resistance precludes instability and destruction of thedevice by second breakdown.

The row of source contacts and the row of drain contacts are staggeredin a direction of the row over a distance equal to a half period of thechannel.

As a result a symmetric layout of the FET is obtained, so that the FETcan be readily scaled to higher voltages and higher ESD currents.

The specific layout of the FET serves to obtain a uniform distributionof the stress current and also to obtain a very compact FET. The layoutis such that a further channel is present which is the mirror image ofthe channel upon reflection in a plane extending at least substantiallyperpendicularly to the semiconductor body and intersecting the row ofsource contacts or the row of drain contacts. The further channel iselectrically parallel-connected to the channel, so that the layout issuitable to drain relatively high currents of several amperes to ground.The higher the voltage peaks to be dealt with by the FET, the moreelectrically parallel-connected channels are necessary. The symmetriclayout enables proper scaling in combination with a comparatively smallactive surface of the FET. It is very advantageous that the spaceoccupied by the FET is reduced as compared to the prior art.Particularly with ICs having a comparatively small surface of severalmillimeters, such as DC-DC converters, much space can be saved becausethe FET occupies a substantial part of the chip surface.

As the source and drain contacts are centered in the source and draindiffusion zones enclosed by the channel and the further channel, thecurrent paths between a source contact and a drain contact are identicalfor all periods of the channel.

It is possible that the source diffusion zones are of a firstconductivity type and are mutually separated by a zone of a secondconductivity type. However, the source diffusion zones are electricallyinterconnected, for example, by means of a metallization pattern. As thesource diffusion zones are electrically interconnected, an ESD eventtriggers a source-zone cascade. By virtue thereof, snap-back does notoccur locally but over a large surface area. The current is distributedmore uniformly over the surface of the FET.

A plurality of contacts may be present per source or drain zone. As aresult, the influence of contact resistances is reduced.

In general ICs having MOS or BiCMOS transistors are protected by aMOSFET. The ESD device and the MOS transistors of the IC aremanufactured simultaneously.

On the active area of the semiconductor body there is a dielectric and agate structure. The gate is electrically insulated from thesemiconductor body by the dielectric. The gate is used as a masking forthe implantations of the source and drain zones. After diffusion of thesource and drain zones, the channel is formed below the gate.

As the channel is self-aligned with respect to the gate, the channelfollows the periodic structure of the gate.

In general, the gate is formed from a layer of highly doped polysilicon.The sheet resistance of the gate can be reduced typically by a factor of50 by using silicidized polysilicon instead of non-silicidizedpolysilicon. This large reduction of the gate resistance precludes theso-termed gate lifting. Owing to the overlap capacitance between thedrain and the gate there is a risk of gate-potential lifting at highdrain voltage changes. The potential of the gate may be lifted, forexample, upon switching another transistor (such as a PMOS transistor)in an output buffer. As a result of switching-off, a dV/dt develops onthe FET which causes the gate voltage to be lifted. A short RC delay asa result of a small gate resistance additionally has the advantage of ashort RC delay enabling rapid switching of the FET. At a low gateresistance the charge is directly drained to ground and the gate voltageremains substantially 0 V. A substantial advantage of a silicidized gateresides in that no special protection mask is necessary duringsilicidation of the ESD protection. As a result, one masking step can besaved. In addition, the extra tolerances built in for aligning the maskare no longer necessary. Without said protection mask, both space andcosts can be saved.

A further reduction of the gate resistance is achieved in that the gate,like the channel, has a mirror image forming a further gate, each periodof the gate being electrically parallel-connected to a period of itsmirror image.

Preferably, the connection between a period of the gate and its mirrorimage is made of a material which is identical to that used for the gateand the further gate. The connections are formed concurrently with thedefinition of the gate and the further gate. A very suitable material ispolysilicon with a high doping of for example As, P, Sb or B.

In a preferred embodiment, the periodic structure of the channel ismeander-shaped.

As a result of the meander shape of the channel, the width of thechannel per unit area is increased. Also the length and the width of thechannel are accurately defined.

In accordance with an advantageous method, the power switch inaccordance with the invention can be electrically connected by means ofan NMOS transistor in a grounded gate configuration, wherein thesemiconductor body comprises a low-impedance substrate which iselectrically connected to ground. In the case of an ESD voltage pulse,the potential on the drain can freely fluctuate relative to thesubstrate, as a result of which a substantial reduction of the parasiticdrain-substrate capacitance is achieved.

These and other aspects of the power switch in accordance with theinvention will be elucidated with reference to the embodiment(s)described hereinafter.

In the drawings:

FIG. 1 diagrammatically shows the position of the power switch inaccordance with the invention on a chip;

FIG. 2 is a plan view of an embodiment of the power switch in accordancewith the invention;

FIG. 3 shows zone A in FIG. 2 on an enlarged scale;

FIG. 4 is a cross-sectional view through B-B in FIG. 2;

FIG. 5 is a cross-sectional view through C-C in FIG. 2;

FIG. 6 diagrammatically shows the power switch in accordance with theinvention in a test setup according to the Human Body Model;

FIG. 7 diagrammatically shows a grounded gate NMOS device configuration;

FIG. 8 shows an embodiment of the power switch in accordance with theprior art;

FIG. 9 shows an avalanche breakdown characteristic;

FIG. 10 graphically shows the influence of the width of the gate on theESD current;

FIG. 11 graphically shows the influence of silicidation on the ESDcurrent.

The NMOS transistor shown in FIG. 1 is a power switch in an outputbuffer. The NMOS also serves to limit the voltage that may develop atthe output of the integrated circuit as a result of an undesirable, highvoltage peak. The NMOS transistor is ESD-robust. In the case of an ESDdischarge the NMOS transistor can suitably be used to remove the ESDcurrent via a known path. In the case of comparatively small ICs, suchas DC-DC converters having a surface area of only a few mm, aconsiderable percentage of the surface (as high as 50%) is occupied bythe ESD protection.

The power switch in accordance with the invention, as shown in FIG. 2,is a MOSFET 1.

The FET 1 comprises an active area 2 in a semiconductor body 3, achannel 4 formed in the active area 2 and having a periodic structure,and source diffusion zones 5 and drain diffusion zones 6 in said activearea 2.

A source diffusion zone 5 is separated from a drain diffusion zone 6 bya half period 7 of the periodic structure of the channel 4. Each sourcediffusion zone 5 has a source contact 8 and each drain diffusion zone 6has a drain contact 9.

The source contacts 8 and drain contacts 9 each form a row 10, 11 in adirection transverse to the plane of symmetry 12 of the channel. Betweena source contact 8 and a drain contact 9 associated with a sourcediffusion zone 5 and a drain diffusion zone 6 which alternate with eachother, current paths are subject to an at least substantially equalseries resistance.

In the embodiment shown in FIG. 2, the periodic structure of the channelis a meander. The channel of the MOSFET has a length of 0.5 μm. Theoverall width of the channels is 600 μm. The meandering channel has aperiod of 4.2 μm. The row of source contacts 10 are situated on theleft-hand side of the first meandering channel. The row of draincontacts 11 on the right-hand side of the first channel are shifted by2.1 μm with respect to the row of source contacts 10. If an ESD eventcauses a voltage to be applied to the drain contacts, then an ESDcurrent starts flowing between the source and the drain. The currentpaths between a source 8 and a drain 9 contact associated with a period7 of the meander cross the channel 4 transversely at differentlocations. As the series resistance for each current path is the same,the current distribution over a period 7 of the channel is very uniform.

FIG. 3 diagrammatically shows the current paths I₁, I₂ between a sourcecontact 8 and a drain contact 9. The row of source contacts 10 and therow of drain contacts 11 are situated outside the area 13 that isclamped by the periodic structure of the channel 4. In the embodimentshown, the series resistance in each current path I₁, I₂ of the sourceand drain zones jointly amount to approximately 8 times the sheetresistance of the source and drain diffusion zones.

The layout of the FET in FIG. 2 is very compact as a result of the highdegree of symmetry. There is a further channel 14 that is the mirrorimage of the channel 4 upon reflection in a plane that extends at leastsubstantially perpendicularly to the semiconductor body 3 and intersectsthe row of source contacts 10 or the row of drain contacts 11. As thefurther channel 14 is electrically parallel-connected to the channel 4,comparatively high ESD currents can be drained to ground.

The source 8 and drain 9 contacts are centered in the source 5 and drain6 diffusion zones which are enclosed by the channel 4 and the furtherchannel 14. The shortest distance from the source or drain contact tothe meandering channel is only 1 μm. Unlike the prior art, where thedistance from the drain contact to the channel is 4.5 μm, in theembodiment shown only 1 μm is necessary. This means an enormous savingin active surface area.

The dotted squares in FIG. 3 indicate that a plurality of contacts 16,17, 18, 19 may be present per source or drain zone. The minimum distanceto the meandering channel is determined by the design rules (0.6 μm inthis example).

The gate 20 is electrically insulated from the channel 4. The channel 4below the gate 20 has the same periodic structure as the gate 20.

Both the source 5 diffusion zones and the drain 6 diffusion zones areelectrically interconnected by an interdigitated metallization patterninterconnecting, respectively, the row of source contacts 10 or the rowof drain contacts 11.

FIG. 4 is a cross-sectional view of the NMOSFET. On a highly dopedp-type substrate an active area 2 is formed in the semiconductor body 3which is surrounded by insulating material, such as SiO₂. The activearea 2 is doped with boron. On the surface of the semiconductor bodythere is provided a gate dielectric of 10 nm SiO₂. Subsequently, a layerof polysilicon having a thickness of 250 nm is deposited. The layer ofpolysilicon is patterned and forms the gate 20. The shallow source anddrain diffusion zones forming an extension of the source 5 and drain 6are implanted with p ions in a dose of 4e13 at/cm² with an energy of 25keV. The source 5 and drain 6 diffusion zones are implanted with As ionsin a dose of 4e15 at/cm² at an energy of 100 keV. The sheet resistanceof the non-silicidized n-type As zone is 55 Ohm/square afteroutdiffusion.

The polysilicon gate 20 is doped concurrently with the source and draindiffusion zones. The sheet resistance of the As-doped polysilicon is 135Ohm/square. After spacer formation next to the polysilicon gate 20, aTi/TiN multilayer is provided in a thickness of 30 nm/25 nm. During arapid thermal process (RTP) there is formed in N₂ at 730° C. in 20seconds approximately 70 nm TiSi₂ on the gate and on the source anddrain diffusion zones. The sheet resistance of the silicidizedpolysilicon is 2.3 Ohm/square. The sheet resistance of the silicidizedsource and drain diffusion zones is 2.3 Ohm/square.

The contacts to the active area are made using W plugs in a manner knownto those skilled in the art. The source contacts are interconnected bymeans of an Al metallization pattern. The drain contacts are alsointerconnected by means of an Al metallization pattern, bothmetallization patterns forming a finger structure.

In FIG. 5, the connection 25 between a period 23 of the gate and itsmirror image 24 is shown for the NMOSFET. The connection is madeconcurrently with the gate 20 and the further gate 21 from polysilicondoped with As in a concentration of 4e15 at/cm². The polysilicon gate20, 21 are doped concurrently with the source and drain diffusion zones.The sheet resistance of the As-doped polysilicon is 135 Ohm/square. Then-type source 5 diffusion zones are electrically insulated from eachother by a p-epi area 15.

In a Human Body Model test setup shown in FIG. 6 a, the NMOS transistoris tested for ESD robustness. A voltage of 2000-8000 V is applied acrossthe 100 pF capacitance. The voltage is discharged across the 1.5 kOhmresistor and the NMOS transistor. At a certain voltage, i.e. the triggervoltage Vtr, the avalanche current is large enough, as a result ofbreakdown of the drain-substrate junction, to turn on the bipolartransistor. As soon as the parasitic bipolar transistor goes intoconduction, snap-back occurs causing the voltage to decrease to theso-termed hold voltage V_(H). FIG. 6 b diagrammatically shows the seriesresistances in the source and drain diffusion zones of different currentpaths. The sum of the series resistances between a source and a draincontact is, in the embodiment shown in FIG. 2, approximately 8 times thesheet resistance of the silicidized source and drain diffusion zones. Itis schematically shown that, dependent upon the current path, the sourcediffusion resistance 27 may exceed the drain diffusion resistance 28.The essence of the invention is that the sum of the source diffusionresistance 27 and the drain diffusion resistance 28 is at leastsubstantially equal for all current paths. As soon as the hold voltageV_(H) is reached, it does not matter, from an electrical point of view,whether the diffusion resistance is present in the source diffusion zoneor in the drain diffusion zone.

The sum of the resistances in the silicidized diffusion zonescorresponds to a series resistance of 8*2.3 Ohm=18.4 Ohm. In theembodiment shown, there are 8*4=32 sections, so that the seriesresistance of the transistor is approximately 600 mOhm.

In the Human Body Model test, the NMOS transistor is robust tovoltages >2000 V. As regards ESD sensitivity, the transistor belongs toclass 2 of the Human Body Model. The resistance of the transistor is 5Ohm in the on-state and the series resistance is 600 mOhm. The totalsurface of the active area is 2043 squares.

In operation, the NMOSFET is connected in a grounded NMOS configurationas shown in FIG. 7. It is remarkable that instead of a p-well contact asused in conventional structures, a highly doped p-type substrate of 0.01Ohm/cm is connected to ground as the rear side contact. The contactingof the p-type substrate has substantial advantages in comparison withthe p-well. In the first place, the space occupied by the p-wellcontacts is saved. What is more important is that also the parasiticcapacitance of the drain to the substrate is absent. The potential ofthe drain zones can freely fluctuate with respect to the substrate. As aresult of the comparatively large surface of the drain diffusion zones,this means that a substantial reduction of the parasitic drain-substratecapacitance is achieved.

The layout of the FET shown in FIG. 2 is much more compact than theconventional finger structure. FIG. 8 shows a conventional fingerstructure which is ESD robust to voltage peaks between 2000-5000 V. Thewidth of the channel of the transistor is 500 μm. The resistance of thetransistor in the on-state is 6 Ohm and the series resistance is 600mOhm.

In the conventional finger structure additional series resistance iscreated by means of an additional mask 30 to block the silicidation ofthe source, the gate and the drain. The protection mask overlaps thepolysilicon gate by 4 μm on the drain side and by 1.7 μm on the sourceside. This not only takes up much space but also causes the resistanceof the gate to be increased by a factor of 50. As a result, the gate ofa large transistor may be locally lifted if the voltage on the drainexhibits a steeply increasing slope. This may lead to a large,undesirable current peak that may seriously interfere with the operationof the chip. This in turn requires additional layout measures leading toa further increase of the surface. To deal with voltage peaks in therange between 2000-5000 V, the surface of the conventional fingerstructure is 4145 squares.

The power switch in accordance with the invention, which has 2043squares of active surface, is much more compact. Relative to theconventional structure, a 50% saving of surface is obtained.

The uniformity of the current in the layout in accordance with theinvention is substantially improved as compared to the conventionalfinger structure. In the conventional finger structure each one of thefingers might be turned on if the voltage rises to the trigger voltage.After a finger starts conducting the bipolar npn transistor and is fixedat the snap-back voltage, the pad voltage is built up as a result of theseries resistance. When the voltage again reaches Vtr the next finger isturned on, etc., until all the fingers are turned on or the failurecurrent is reached, whichever of the two occurs first. In general, themaximum current for failure is reached first and the number of fingersthat are really turned on vary substantially.

The avalanche breakdown characteristic for the NMOSFET in accordancewith the first embodiment is shown in FIG. 9. As a result of the highpositive drain voltage, avalanche multiplication occurs in the depletionzone of the drain junction. As the surface concentration of the drainexceeds that in the bulk, typically 1e20 at/cm², breakdown occurs at theedge of the drain junction. The threshold voltage Vtr for breakdown as aresult of avalanche multiplication is approximately 12 V. As a result ofthe substrate current the source-substrate diode becomes conducting. Theparasitic bipolar transistor is turned on. As a result of the conductionby the bipolar transistor the electrons are led to the drain. The holdvoltage V_(H) is approximately 6 V. After the npn is turned on and keepsthe voltage at approximately 6 V, the voltage of the pad can increase tothe 12 V trigger voltage as a result of the series resistance.

FIG. 10 shows that the ESD current depends substantially linearly on thewidth of the channel. Breakdown at the surface of the inhibiteddrain-substrate junction (curve a) occurs sooner than breakdown causedby self-heating (curve b).

FIG. 11 shows the influence of silicidation on the ESD current. As thesheet resistance of the drain is substantially reduced from 55 Ohm inthe non-silicidized case to 2.3 Ohm in the case where 70 nm TiSi₂ isformed, only a maximum current of 0.6 A can be drained to ground by thetransistor (curve c). Without silicide, the maximum current isapproximately 2 A (curve d).

1. A power switch comprising a field effect transistor (FET) includingan active area in a semiconductor body, a channel formed in said activearea and having a periodic structure, source diffusion zones and draindiffusion zones in the active area, a source diffusion zone beingseparated from a drain diffusion zone by a half period of the periodicstructure of the channel, and each source diffusion zone having a sourcecontact, and each drain diffusion zone having a drain contact,characterized in that the source contacts and the drain contacts eachform a row in a direction transverse to the plane of symmetry of thechannel, current paths being subject to substantially equal seriesresistance between a source contact and a drain contact associated witha source diffusion zone and a drain diffusion zone which alternate witheach other.
 2. A power switch as claimed in claim 1, characterized inthat the periodic structure of the channel clamps an area, the row ofsource contacts and the row of drain contacts being situated outside theclamped area.
 3. A power switch as claimed in claim 1, characterized inthat the row of source contacts and the row of drain contacts arestaggered in a direction of the row over a distance equal to a halfperiod of the channel.
 4. A power switch as claimed in claim 1,characterized in that a further channel is present which is the mirrorimage of the channel upon reflection in a plane extending at leastsubstantially perpendicularly to the semiconductor body and intersectingthe row of source contacts or the row of drain contacts, and saidfurther channel being electrically parallel-connected to the channel. 5.A power switch as claimed in claim 3, characterized in that the sourceand drain contacts are centered in the source and drain diffusion zonesenclosed by the channel and the further channel.
 6. A power switch asclaimed in claim 1, characterized in that the source diffusion zones areof a first conductivity type and are mutually separated by a zone of asecond conductivity type.
 7. A power switch as claimed in claim 1,characterized in that a plurality of contacts are present per source ordrain zone.
 8. A power switch as claimed in claim 1, characterized inthat above the channel there is a gate that is electrically insulatedfrom the channel, said gate following the periodic structure of thechannel.
 9. A power switch as claimed in claim 8, characterized in thatthe gate is silicidized.
 10. A power switch as claimed in claim 8,characterized in that the gate, like the channel, has a mirror imageforming a further gate, a period of the gate being electricallyparallel-connected to a period of its mirror image.
 11. A power switchas claimed in claim 8, characterized in that the connection between aperiod of the gate and its mirror image is made of a material which isidentical to that used for the gate and the further gate.
 12. A powerswitch as claimed in claim 1, characterized in that the periodicstructure is a meander.
 13. A method for using the power switch asclaimed in claim 1, wherein the FET is an NMOS which is electricallyconnected in a grounded gate configuration, and wherein thesemiconductor body comprises a low-impedance substrate which iselectrically connected to ground.